Detection of Module Integration Errors in Hierarchical Circuit Designs Nicholas Dematteis, Jesus Godinez, Gina Rhoads, and Maddu Karunaratne, University of Pittsburgh, USA
Power Evaluation of MIPS Architecture using Clock Gating Technique on FPGAs V.Prasanth1, K.Babulu1, and M.Kamaraju2, 1JNTUGV, India, 2Gudlavalleru Engineering College, India
